In conventional common element pixel architecture (CEPA) systems, pixels are configured to utilize common elements such as readout circuitry. These CEPA architectures reduce the amount of hardware necessary for implementing an imager.
Conventional CEPA systems, however, also share a single column line. For example, if adjacent pixel columns are configured to share readout circuitry, they are also configured to share the same column line (i.e. the pixels in each row/group of a respective column are readout sequentially over the same column line). This conventional CEPA system therefore inhibits readout speed of the pixels in the imager.